Semiconductor device using semiconductor chip

ABSTRACT

A semiconductor chip  1  is provided with a first electrode  2  formed at a first corner of a crystal substrate  1   a  generally quadrangular as viewed in plan, and with a second electrode  3  formed to extend along two sides of the crystal substrate  1   a , these sides including between them a second corner located diagonally away from the first corner. The first electrode  2  and the second electrode  3  are connected to a first lead  15  and second leads  16   a   , 16   b  formed on the circuit substrate  10  via solder paste  20 . The narrow first lead  15  extends transversely to a side of the crystal substrate  1   a , and the second leads  16   a   , 16   b  extends in the opposite direction to that of the first lead  15 . The first lead  15  and the second lead  16   b  are offset from each other by an appropriate distance. With such arrangements, the surface tension of melted solder prevents the semiconductor chip  1  from being fixed to the circuit substrate  10  with a slanting posture.

TECHNICAL FIELD

The present invention relates to a semiconductor device utilizing asemiconductor chip, wherein the semiconductor chip has a surfaceprovided with a first electrode and a second electrode, the chip beingsoldered to a pair of external connection electrodes formed on a surfaceof a circuit substrate.

BACKGROUND ART

As disclosed in prior art JP-A-H11-121797 and JP-A-2002-94123, forexample, a conventional surface-mounting light-emitting diodeincorporates a semiconductor chip or light-emitting diode chip(light-emitting element chip) 1, which comprises, as a light source, agallium nitride compound semiconductor, and a crystal substrate made ofsapphire glass having one surface upon which a plurality of thinsemiconductor layers are formed by a known metal-organic chemical vapordeposition method. Such a thin-layer laminate, as shown in FIGS. 1(a)and 1(b), has a double hetero structure including a crystal substrate 1a, rectangular as viewed in plan and made of a transparent sapphireglass, upon which a GaN buffer layer 1 b, an n-type GaN layer 1 c, anInGaN activation layer 1 d, a p-type AlGaN layer 1 e and a p-type GaNlayer 1 f are stacked in this order.

At one corner (vertex portion) of the n-type GaN layer 1 c mentionedabove, an upper portion is removed by etching to provide a step-likeconfiguration. In this removed portion, a p-type electrode 2 (referredto as the “first electrode” below) is formed by vapor deposition, theelectrode comprising a laminate of Ti and Au layers and another laminateof Ni and Au layers stacked on the first laminate. In a portion otherthan the etched-away portion, the upper surface of the uppermost p-typeGaN layer if is provided with a p-type electrode 3 (referred to as the“second electrode” below) comprising a laminate of Ni and Au layers andproduced by vapor deposition like the above.

According to the prior art technique, a bump made of gold (Au) is formedon each of the first electrode 2 and the second electrode 3 of thelight-emitting element chip 1. These bumps are fixed to a pair ofexternal connection electrodes formed on a chip-type circuit substrate.

However, the production cost tends to be unduly high since the bumps aremade of gold (Au). Another problem results from the way in which thelight-emitting chip 1 (semiconductor chip) is pressed against thecircuit substrate and connected to the external connection electrodesvia the bumps. In this manner, the light-emitting chip is fixed to thecircuit substrate, with its original posture remaining as it comes closeto the substrate, so that the mounting-posture variation described belowcannot be corrected.

In place of such metal bumps, it was proposed to use a thermallymeltable die-bonding agent, such as solder paste, for connection.Specifically, an appropriate amount of die-bonding agent is applied tothe external connection electrodes of the circuit substrate, and thesemiconductor chip is placed onto the applied die-bonding agent. In thisstate, the die-bonding agent is heated to melt, and then caused tosolidify. This method, however, gives rise to the following problems.

As noted above, the die-bonding agent applied to the external connectionelectrodes is heated to melt. At this time, the agent spreads in alldirections over each electrode. The semiconductor chip, supported on themelted die-bonding agent, tends to deviate laterally from the prescribedcenter over the connection electrodes, and thereafter the chip is fixedto the electrodes at the off-center position upon solidifying of thedie-bonding agent.

In this connection, it should be noted that each of the conventionalexternal connection electrodes formed on the circuit substrate has alarge surface area, and hence an unacceptably gross deviation canresult.

Further, supposing that the semiconductor chip is placed on the externalconnection electrodes, with the right and left edges of the rectangularsemiconductor chip being held in non-parallel condition (slantcondition) relative to the right and left edges of the rectangularcircuit substrate, the slant posture is not corrected, and therefore thefixing to the external connection electrodes is performed in thenon-parallel condition.

Accordingly, when the semiconductor chip, die-bonded to the externalconnection electrodes of the circuit substrate, is covered by moldpackaging of a synthetic resin, it is necessary to consider two cases,i.e. the off-center deviation of the semiconductor chip to be packagedand the non-parallel relationship between the edges of the chip and theedges of the circuit substrate. In either case, the mold needs to belarge to ensure proper packaging, and this makes the semiconductordevice unduly large and heavy.

In particular, when the semiconductor device is a chip LED comprising alight-emitting diode chip and a transparent synthetic resin modle, theoff-center deviation of the semiconductor chip and the non-parallelrelationship between the diode chip's edges and the circuit substrate'sedges make different the emitting directions of light from diode chips,resulting in undesired variations in directivity of light.

The technical object of the present invention is to solve theabove-described problems.

DISCLOSURE OF THE INVENTION

To attain the technical object, according to a first aspect of thepresent invention, there is provided a semiconductor device utilizing asemiconductor chip. The device comprises a semiconductor chip providedwith: a first electrode formed in a small region at a first corner onone surface of a crystal substrate generally quadrangular as viewed inplan; and a second electrode formed in a large region and facing thefirst electrode. The second electrode is arranged to cover a secondcorner located diagonally away from the first corner and extend alongtwo sides of the crystal substrate that include the second corner. Thesemiconductor device also comprises a circuit substrate including anupper surface provided with a pair of external connection electrodesconnected to the first electrode and the second electrode via athermally meltable die-bonding agent such as solder paste. The externalconnection electrodes may comprise: a first external connectionelectrode including a first lead connected to the first electrode; and asecond external connection electrode including a second lead connectedto the second electrode. The first lead of the first external connectionelectrode may be narrow and extend transversely to one side of thecrystal substrate. The second lead of the second external connectionelectrode may include at least one narrow strip and extend in adirection opposite to the extending direction of the first lead. Thesecond lead may be transverse to another side of the crystal substratethat is generally parallel to said one side to which the first lead istransverse. The first lead and the second lead may be offset from eachother by a prescribed distance.

According to a second aspect of the present invention, there is provideda semiconductor device utilizing a semiconductor chip. The device maycomprise a semiconductor chip provided with: a first electrode formed ina small region at a first corner on one surface of a crystal substrategenerally quadrangular as viewed in plan; and a second electrode formedin a large region and facing the first electrode. The second electrodemay be arranged to cover a second corner located diagonally away fromthe first corner and extend along two sides of the crystal substratethat include the second corner. The semiconductor device may alsocomprise a circuit substrate including an upper surface provided with apair of external connection electrodes connected to the first electrodeand the second electrode via a thermally meltable die-bonding agent suchas solder paste. The external connection electrodes may comprise: afirst external connection electrode including a first lead connected tothe first electrode; and a second external connection electrodeincluding a second lead connected to the second electrode. The firstlead of the first external connection electrode may be narrow and extendtransversely to one side of the crystal substrate. The second lead ofthe second external connection electrode may include at least one narrowstrip and extend in a direction opposite to the extending direction ofthe first lead. The second lead may be transverse to another side of thecrystal substrate that is generally parallel to said one side to whichthe first lead is transverse. The second lead may be provided, at an endthereof, with a front electrode piece which is connected to the secondelectrode and parallel to but offset by a prescribed distance from thefirst lead.

In the inventions according to the first and the secondaspects,thermally meltable die-bonding agent such as solder paste is applied tothe first and the second external connection electrodes on the circuitsubstrate, and then these electrodes are aligned with the relevant oneof the first electrode and the second electrode of the semiconductorchip.

In the above procedure, the first external connection electrode is to beconnected to the first electrode formed in a small region at a firstcorner of the semiconductor chip, while the second external connectionelectrode is to be connected to the second electrode having a largearea, the second electrode being arranged to surround the firstelectrode of the semiconductor chip and to cover a second corner locateddiagonally away from the first corner.

With this arrangement, melted die-bonding agent will spread over eachexternal connection electrode in all directions, in particular, over thesurface of the narrow lead to flow away from a side of the semiconductorchip (the crystal substrate) At the crossing point of each lead and therelevant side of the semiconductor chip, the melted die-bonding agentwill flow along the relevant side of the chip. At this stage, thesurface tension of the melted die-bonding agent simultaneously acts onboth the lead and the crossing side of the semiconductor chip (crystalsubstrate). As a result, the self-alignment for automatic postureadjustment is performed so that the crossing angle between thelongitudinal direction of each lead and the relevant side of the crystalsubstrate becomes generally 90°.

According to the first aspect of the present invention, the second leadis offset from the first lead by an appropriate distance so that theextension line of the second lead passes a point close to the arealcenter of the semiconductor chip as viewed inplan. Accordingly, thefirst lead (the first external connection electrode) overlaps the firstelectrode at a corner which is distant from the center of thesemiconductor chip. Thus, the position at which the first lead projectsfrom the relevant side of the semiconductor chip is farther away fromthe areal center of the semiconductor chip than the position at whichthe second lead projects from the relevant side of the semiconductorchip is. As a result, the moment due to the above-mentioned surfacetension (the force that rotates the semiconductor chip about its center)becomes greater with respect to the first lead. This contributes torealizing effective automatic posture correction so that the crossingangle between the longitudinal direction of the first and second leadsand the opposing sides of the crystal substrate is adjusted to becomegenerally 90°, even when the opposing sides of the crystal substratetransverse to the longitudinal direction of the first and the secondleads are non-perpendicular and non-parallel to the longitudinaldirection of each lead (i.e. in slanting position).

As described above, due to the self-alignment by the surface tension ofthe melted die-bonding agent, the quadrangular semiconductor chip issubjected to automatic adjustment for correcting the slanting postureand for accurately positioning the chip to the center of the circuitsubstrate.

In this state, the melted die-bonding agent is allowed to cool forsolidification, thereby fixing the semiconductor chip to the substratewith the automatically corrected posture. According to the second aspectof the present invention, the second external connection electrode isformed with at least one second lead which is narrow and extends in thedirection opposite to the extending direction of the first lead, andwhich extends transversely to a side of the crystal substrate that isgenerally parallel to the side the first lead crosses. The second leadis provided, at its front end, with a front electrode piece which isconnected to the second electrode and parallel to, but offset by anappropriate distance from, the first lead. Accordingly, the melteddie-bonding agent spreads through the gap present between the frontelectrode piece and the second electrode of the semiconductor chip. Atthe same time, it spreads through the gap between the first lead and thefirst electrode. Then, the surface tension working at the frontelectrode piece and the surface tension working at the first lead willbalance out on two sides flanking the areal center of the semiconductorchip as viewed in plan. Thus, the self-alignment by the surface tensionof the melted die-bonding agent automatically corrects slanting postureof the semiconductor chip, while also automatically positioning thesemiconductor chip to the center of the circuit substrate with accuracy.

According to a third aspect of the present invention, there is provideda semiconductor device utilizing a semiconductor chip, the devicecomprising a semiconductor chip provided with: a first electrode formedin a small region at a central portion along one side on one surface ofa crystal substrate generally quadrangular as viewed in plan; and asecond electrode formed in a large region and facing the firstelectrode, the second electrode extending along other three sides of thecrystal substrate. The device also comprises a circuit substrateincluding an upper surface provided with a pair of external connectionelectrodes connected to the first electrode and the second electrode viaa thermally meltable die-bonding agent such as solder paste. Theexternal connection electrodes comprises: a first external connectionelectrode including a first lead connected to the first electrode; and asecond external connection electrode including a second lead connectedto the second electrode. The first lead of the first external connectionelectrode is narrow and extends transversely to one side of the crystalsubstrate. The second lead of the second external connection electrodeincludes at least one narrow strip and extends in a direction oppositeto the extending direction of the first lead, the second lead beingtransverse to another side of the crystal substrate that is generallyparallel to the above-mentioned one side to which the first lead istransverse.

According to the third aspect of the present invention, the firstelectrode is disposed at a generally central position along one side ofthe generally quadrangular crystal substrate, while the second electrodeis arranged to face the first electrode and extend along the other threesides of the crystal substrate. Thus, both of the first electrode andthe second electrode are laterally symmetrical on the semiconductor chipas viewed in plan. The first lead, which overlaps the first electrode,extends in the direction opposite to the extending direction of thesecond lead, which overlaps the second electrode. Accordingly, at thecrossing portions between two opposing parallel sides of thesemiconductor chip and the leads, the melted die-bonding agent spreadsnot only along the sides of the semiconductor chip, but also along theelongated leads. Since the surface tension of the melted die-bondingagent acts simultaneously on the respective leads and on the sides ofthe semiconductor chip (the crystal substrate) which are crossed by theleads, the self-alignment can be enjoyed to effectuate automatic posturecorrection so that the crossing angle between the longitudinal directionof each lead and the crossed side of the crystal substrate becomesgenerally 90°. In this way, it is possible to adjust the posture of thesemiconductor chip to be mounted on the circuit substrate.

In each of the above-mentioned inventions, the second lead of the secondexternal connection substrate may be provided, at an end thereof, with afront electrode piece which extends transversely to the longitudinaldirection of the second lead and which is connected to the secondelectrode. With such an arrangement, the front electrode piece providesa larger electrical contact area with respect to the second electrode.Further, at this portion (the front electrode piece), the surfacetension of the melted die-bonding agent contributes to the posturecorrection of the semiconductor chip by the self-alignment.

Further, in each invention described above, the second externalconnection electrode may be formed with a third lead integral therewith.The third lead extends generally in parallel to a side of the crystalsubstrate which is perpendicular to another side of the same substratewhich is crossed by the second lead. The third lead is provided with afront end which crosses the first-mentioned side of the substrate andwhich is connected to the second electrode. Specifically, the third leadis L-shaped as viewed in plan, having a base end connected to the secondexternal connection electrode and a front end which extends transverselyto the longitudinal direction of the second lead to be connected to thesecond electrode. With such an arrangement, besides the self-alignmenteffect by the first and the second leads, the additional self-alignmenteffect can be enjoyed due to an interaction between the front end of thethird lead and the side of the crystal substrate which is parallel tothe longitudinal direction of the respective leads. Accordingly, theself-alignment effect is improved, whereby the posture adjustment of thesemiconductor chip is more reliably performed.

Further, in each invention described above, the first lead, the secondlead and the third lead may have a width which is about 0.1-0.3 timesthe length of the opposing sides of the crystal substrate. With such anarrangement, the melted die-bonding agent can easily spread along a sideextending longitudinally of each lead, whereby the posture adjustment ofthe semiconductor chip by the self-alignment is much more reliablyperformed.

Further, in each invention described above, the semiconductor chip maybe a light-emitting element, and at least the semiconductor chip may bepackaged by a transparent, synthetic resin mold. With such anarrangement, it is possible to adjust the posture of the light-emittingelement mounted on the circuit substrate, thereby eliminating thevariations in emitting direction of light (directivity of light) fromthe light-emitting element. Also, the mold for packaging thesemiconductor chip is made smaller than is conventionally possible.Accordingly, the semiconductor device can be reduced in size and weight.

Further, in each invention described above, a resist layer may be formedon parts of the first, second and third leads, the parts being close toa periphery of the semiconductor chip. With such a resist layer, it ispossible to prevent the die-bonding agent from flowing in thelongitudinal direction of the lead outwardly from the periphery of thesemiconductor chip, whereby the occurrence of improper electricalconnection is reliably prevented.

Further, the resist layer may be provided with a highly reflective colorsuch as white, so that light emitted from the light-emitting element andreflected toward the upper surface of the circuit substrate is reflectedby the resist layer, whereby efficient chip light-emitting diodes can beprovided.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1(a) is a top view showing a light-emitting chip used for a firstembodiment of the present invention, while FIG. 1(b) is a sectional viewtaken along lines Ib-Ib in FIG. 1(a).

FIG. 2 is a perspective view showing a chip LED according to a firstembodiment.

FIG. 3 is a plan view showing the chip LED of the first embodiment.

FIG. 4 is a sectional view taken along lines IV-IV in FIGS. 2 and 3.

FIG. 5 is a sectional view taken along lines V-V in FIGS. 2 and 3.

FIG. 6(a) is a plan view showing the light-emitting diode chip placed ona circuit substrate in the first embodiment, while FIG. 6(b) is a planview showing the light-emitting chip whose position has been adjusteddue to the solidification of a die-bonding agent.

FIG. 7(a) is a plan view showing the arrangement of a resist layer in asecond embodiment, while FIG. 7(b) is aplanview showing a light-emittingchip whose position has been adjusted due to the solidification of adie-bonding agent.

FIG. 8(a) is a plan view showing a light-emitting diode chip planed on acircuit substrate in a third embodiment, while FIG. 8(b) is a plan viewshowing the diode chip whose position has been adjusted due to thesolidification of a die-bonding agent.

FIG. 9(a) is a plan view showing the arrangement of a resist layer in afourth embodiment, while FIG. 9(b) is aplanview showing a light-emittingchip whose position has been adjusted due to the solidification of adie-bonding agent.

FIG. 10(a) is a plan view showing a light-emitting diode chip planed ona circuit substrate in a fifth embodiment, while FIG. 10(b) is a planview showing the diode chip whose position has been adjusted due to thesolidification of a die-bonding agent.

FIG. 11(a) is a plan view showing the arrangement of a resist layer in asixth embodiment, while FIG. 11(b) is a plan view showing alight-emitting chip whose position has been adjusted due to thesolidification of a die-bonding agent.

FIG. 12 is a planview showing a light-emitting diode chip whose positionhas been adjusted due to the solidification of a die-bonding agent.

BEST MODE FOR CARRYING OUT THE INVENTION

Preferred embodiments for carrying out the present invention will bedescribed below with reference to the drawings illustrating chip LEDs asan example of semiconductor device. FIGS. 1-6 show a first embodiment.The chip LED includes a circuit substrate 10 as an insulating substrate,a light-emitting diode chip 1 as an example of semiconductor chipmounted on the upper surface of the substrate, and a mold 19 made of atransparent synthetic resin and provided on the upper surface of thesubstrate 10 for entirely covering the light-emitting diode chip 1 (seeFIG. 2).

The chip mounting is performed in a manner such that a thermallymeltable die-bonding agent such as solder paste is applied to a firstexternal connection electrode 13 and a second external connectionelectrode 14, both formed on the insulating circuit substrate 10 whichis quadrangular (including square and rectangular; the same applieshereinafter) as viewed in plan. Then, the semiconductor chip, turnedupside down from the state shown in FIG. 1, is moved so that the firstelectrode 2 and the second electrode 3 are placed onto the correspondingparts of the applied agent, and heated. Thereafter, as the die-bondingagent solidifies, the semiconductor chip is fixed, and the electricalconnection is completed (see FIG. 4).

As an example of semiconductor chip, the light-emitting diode chip(light-emitting element) 1 shown in FIGS. 1(a) and 1(b) is substantiallythe same in structure as the conventional one (previously described).Specifically, use is made of a crystal substrate 1 a, which is made oftransparent sapphire and formed quadrangular (including square andrectangular; the same applies hereinafter) as viewed in plan, and uponwhich a GaN buffer layer 1 b, an n-type GaN layer 1 c, an InGaNactivation layer 1 d, a p-type AlGaN layer 1 e, and a p-type GaN layer 1f are stacked, providing a double hetero structure.

At one corner, an upper portion of the n-type GaN layer 1 c is removedby etching to provide a step portion. In the removed portion, an n-sideelectrode or first electrode 2 is formed by vapor deposition, whichconsists of a laminate of Ti and Au layers and another laminateconsisting of Ni and Au layers stacked on the first laminate. Theremaining portion other than the etched-away portion, in other words,the upper surface of the uppermost p-type GaN layer 1 f is provided witha second electrode 3 consisting of Ni and Au layers formed by vapordeposition, wherein the layer 1 f extends along two edges of the crystalsubstrate 1 a,the edges containing a corner which is located diagonallyopposite to the above-mentioned corner where the first electrode 2 isformed. With such an arrangement, the first electrode 2, formed in arelatively small region at the first-mentioned corner, has a generallypentagonal configuration as viewed in plan, while the second electrode3, formed in a relatively large area (region) separated from the firstelectrode 2 by a generally L-shaped space 4 as viewed in plan, has agenerally L-shaped configuration (see FIG. 1(a)).

The chip-type circuit substrate 10, as shown in FIGS. 2 and 3, is agenerally quadrangular, insulating plate made of glass-fiber-reinforcedepoxy, for example. The circuit substrate 10 has a pair of end portionsopposite to each other, at which a pair of terminal electrodes 11, 12are formed from a metal layer. Each of the terminal electrodes 11, 12extends from the upper surface of the substrate 10 onto the lowersurface via the side surface.

The circuit substrate 10 includes a surface (upper surface) for med witha first external connection electrode 13 connected to the terminalelectrode 11 and a second external connection electrode 14 connected tothe terminal electrode 12, these connection electrodes being formed bypatterning a metal layer.

As shown in FIGS. 2 and 3, the first external connection electrode 13includes one first lead 15 whose base end is formed integral with theterminal electrode 11. The first lead 15 is parallel to the longitudinaledges 10 a, 10 b of the circuit substrate 10. The front end of the firstlead 15 is arranged to overlap with the first electrode 2 of the diodechip 1 as viewed in plan.

The second external connection electrode 14 includes a plurality ofsecond leads 16 a, 16 b and an L-shaped third lead 17, these leadshaving their base ends formed integral with the second terminalelectrode 12. The second leads 16 a, 16 b and the third lead 17 areparallel to the longitudinal edges 10 a, 10 b of the circuit substrate10, wherein at least one of the second leads (in the present embodiment,the second lead 16 b) and the third lead 17 are offset from the firstlead 15 by prescribed distances H1, H2 (see FIG. 3) so that they are notin line. The front ends of the second leads 16 a, 16 b and the thirdlead 17 are arranged to overlap with the second electrode 3 of thelight-emitting diode chip 1 as viewed in plan.

The first lead 15, the second leads 16 a, 16 b and the third lead 17have a small width H3 which is generally 0.3-0.1 times the width of theend portions of the crystal substrate 1 a of the light-emitting diodechip 1, and these leads are formed by patterning to be integral with theupper side portions of the terminal electrode 11 or the terminalelectrode 12.

The first electrode 2 and the second electrode 3 of the diode chip 1 areoverturned to face downward. Then, the first electrode 2 and the secondelectrode 3 are connected to the first lead 15 of the first externalconnection electrode 13 or the second leads 16 a, 16 b and the thirdlead 17 of the second external connection electrode 14 on the circuitsubstrate 10 via a thermally meltable die-bonding agent 20 such assolder paste.

Specifically in the first embodiment, as shown in FIG. 6(a), thethermally meltable die-bonding agent 20 such as solder paste is appliedto the hatched areas generally corresponding in position to the frontends of the first lead 15, the second leads 16 a, 16 b and the thirdlead 17. Then, the light-emitting diode chip 1 is placed on thedie-bonding agent, 20 with the first electrode 2 and the secondelectrode 3 facing downward. In this state, the solder paste for exampleis heated up to a temperature no lower than its melting point, and thenthe die-bonding agent 20 is allowed to cool for solidification.

The light-emitting diode chip 1 is so arranged that the first electrode2 is located on the upper side of the front end of the first lead 15,and that the second electrode 3 is located on the upper sides of thefront ends of the second leads 16 a, 16 b and the third lead 17. Whenthe light-emitting diode chip 1 (the crystal substrate 1 a) is viewed inplan, as seen from FIG. 2, the crystal substrate 1 a has four sides: afirst side 1 a 1, a second side 1 b 2, a third side 1 a 3 and a fourthside 1 a 4. As shown in the plan view of FIG. 6(a), the first lead 15extends to cross the first side 1 a 1 of the quadrangular light-emittingdiode chip 1 (the crystal substrate 1 a), and the second leads 16 a, 16b extend to cross the third side 1 a 3 of the diode chip 1 (the crystalsubstrate 1 a). On the other hand, the third lead 17 has a base partwhich extends in parallel to the fourth side 1 a 4 of the crystalsubstrate 1 a and is located outwards of the fourth side 1 a 4, whilethe front end 17 a (a part of the L-bent member) of the third lead 17extends to cross the fourth side 1 a 4.

When the light-emitting diode chip 1 is mounted onto the circuitsubstrate in the manner described above, the diode chip 1 may be slantedso that the first side 1 a 1 and the fourth side 1 a 4 of the chip 1 arenonparallel to the edges 10 a, 10 b of the circuit substrate 10, asshown by the double-dot chain lines in FIG. 6(a), or the diode chip 1may be located at a position deviating from the center of the circuitsubstrate 10. In such a case, the surface tension of the thermallymelted solder (die-bonding agent) 20 acts simultaneously on therespective crossing portions between the leads 15, 16 a, 16 b, 17 a andthe sides 1 a 1, 1 a 2, 1 a 3, 1 a 4 of the light-emitting diode chip 1.Thus, by the self-alignment effect due to the surface tension, thequadrangular diode chip 1 undergoes automatic posture correction (seeFIG. 6(b)) so that the crossing angle between the longitudinal directionof the first lead 15 and the first side 1 a 1 of the diode chip 1becomes generally 90° as viewed in plan. Likewise, the crossing anglebetween the longitudinal direction of the second leads 16 a, 16 b andthe third side 1 a 3 becomes generally 90° as viewed in plan. Further,the crossing angle between the longitudinal direction of the front end17 a of the third lead 17 and the fourth side 1 a 4 becomes generally90° as viewed in plan. In the present embodiment, the first lead 15 andthe second leads 16 a, 16 b extend in parallel to the longitudinal edge10 a (10 b) of the circuit substrate 10. Accordingly, the postureadjustment is performed so that the first side 1 a 1 of the quadrangulardiode chip 1 becomes parallel to the edge 10 a of the circuit substrate10.

Thereafter, the fixing of the diode chip 1 is performed in the posturecorrected state by the solidification of the melted solder. In apreferred embodiment, it is possible not to use the third lead 17 shownin FIGS. 2-6.

In the embodiment shown in FIG. 6(a), a front portion (the position ofthe part bonded to the first electrode 2) of the first lead 15 and anextension line of the first lead 15 are sufficiently offset from thecenter of the plan view of the diode chip 1 (the crystal substrate 1 a)On the other hand, an extension line of the second lead 16 b and anextension line of the front end 17 a of the third lead 17 come close tothe center of the plan view of the light-emitting diode chip 1.Therefore, the moment resulting from the surface tension (the forcecausing the semiconductor chip to rotate about its central point) isgreater at the side of the first lead 15. Thus, even when the twoopposing sides of the crystal substrate (the first side 1 a 1 and thethird side 1 a 3), which cross the extension lines of the first lead 15and the second lead 16 b, are put in nonparallel position (slantposition), being non-perpendicular to the extension lines of both theleads, the automatic posture correction is executed so that the crossangle between the longitudinal direction of the first and second leads15, 16 a, 16 b and the paired opposing sides (the first side 1 a 1 andthe third side 1 a 3) of the crystal substrate 1 a becomes generally90°. In addition, an automatic correction is made for correctlypositioning the light-emitting diode chip 1 to the areal center of thecircuit substrate 10.

FIGS. 7(a) and 7(b) show a second embodiment, wherein the surfaces(upper surfaces) of the first lead 15, the second leads 16 a, 16 b andthe third lead 17 and the surface of the circuit substrate 10 includeportions close to the periphery of the diode chip 1, in other words,base-adjacent portions (close to the terminal electrode 11 or 12) of therespective leads. These portions are covered by a resist layer 21, andthen, as shown by the hatching in FIG. 7(a), the die-bonding agent 20such as solder paste is applied to areas at and near the front ends ofthe first lead 15, the second leads 16 a, 16 b and the third lead 17.

If much agent were applied to the base-adjacent portions of the leads15, 16 a, 16 b and 17, the applied solder (die-bonding agent) 20 on theleads 15, 16 a, 16 b, 17 would be melted, and the melted solder(die-bonding agent) 20 would be drawn toward them (the base ends). As aresult, the melted solder would flow away to a position where it isseparated from the first electrode 2 and the second electrode 3, andthis would give rise to improper electrical connection between the leadsand the electrodes. However, with the resist layer 21 formed at theabove-described positions, it is possible to prevent the flow of themelted solder in the longitudinal directions of the respective leads.Accordingly, the posture correcting function by the self-alignmenteffect is improved, and no improper electrical connection results. Forthe purposes of checking undesired flow of the melted die-bonding agent20, the resist layer 21 may be applied only to the surface of each lead.Preferably, the resist layer 21 may be provided with a highly reflectivecolor such as white, so that the light emitted from the diode chip 1 canbe reflected by the resist layer 21 on the upper surface of the circuitsubstrate 10, which is advantageous to improving the usability of lightfrom the diode chip.

FIG. 8(a) and FIG. 8(b) show a third embodiment, wherein the first lead15 for the first external connection electrode 13 is the same inposition and configuration as that of the first embodiment and thesecond embodiment. However, use is made of only one second lead 22 forthe second external connection electrode 14, the first lead 15 and thesecond lead 22 being offset from each other by an appropriate distanceH4. Further, the second lead 22 has a front end which is integrallyconnected to a front electrode piece 23, which may be L-shaped andextend transversely to the longitudinal direction of the base portion ofthe second lead 22.

As shown by the hatching in FIG. 8(a), a thermally meltable die-bondingagent 20 such as solder paste is applied to a front part of the firstlead 15 and also applied to or near the second lead 22 and the frontelectrode piece 23. Then, the diode chip 1 is placed on the die-bondingagent 20, with the first electrode 2 and the second electrode 3 facingdownward. In this state, the solder paste for example is heated to atemperature no lower than the melting point, and then the die-bondingagent 20 is allowed to cool for solidification.

In the above-described procedure, the diode chip 1 may be slanted sothat the first side 1 a 1 and the fourth side 1 a 4 of the chip 1 arenonparallel to the edges 10 a, 10 b of the circuit substrate 10, asshown by the double-dot chain lines in FIG. 8(a), or the diode chip 1maybe located at a position deviating from the center of the circuitsubstrate 10. In such a case, the surface tension of the thermallymelted solder (die-bonding agent) 20 acts simultaneously on therespective crossing portions between the leads 15, 22 and the sides 1 a1, 1 a 3 of the light-emitting diode chip 1. Thus, by the self-alignmenteffect due to the surface tension, the quadrangular diode chip 1undergoes automatic posture correction (see FIG. 8(b)) so that thecrossing angle between the longitudinal direction of the first lead 15and the first side 1 a 1 of the diode chip 1 becomes generally 90° asviewed in plan. Likewise, the crossing angle between the longitudinaldirection of the second lead 22 and the third side 1 a 3 becomesgenerally 900 as viewed inplan. Further, in the presence of the frontelectrode piece 23 of the second lead 22, a proper electrical connectionis made with respect to the second electrode 3.

FIG. 9(a) and FIG. 9(b) show a fourth embodiment provided with the sameleads as the leads 15, 22 by the third embodiment and with a resistlayer 21 formed around the diode chip 1 on the circuit substrate 10,whereby the advantages of the third embodiment and the advantages of thesecond embodiment (see FIG. 7(a) and FIG. 7(b)) can be enjoyed.

FIG. 10(a) and FIG. 10(b) show a fifth embodiment, wherein the firstlead 15 of the third embodiment and the base portion of the second lead22 are arranged in line, as viewed in plan. The second lead 22 has afront portion which integrally includes a first front electrode piece 23a extending generally perpendicularly to the longitudinal direction ofthe base portion of the second lead 22, and a second front electrodepiece 23 b extending generally perpendicularly to the first frontelectrode piece 23 a, as viewed in plan, wherein the second frontelectrode piece 23 b is offset from the first lead 15 by an appropriatedistance H5. The first front electrode piece 23 a and the second frontelectrode piece 23 b are provided at a position allowing them to beconnected (overlap) to the second electrode 3 of the diode chip 1 (thecrystal substrate 1 a).

In the above-described arrangement, as shown by the hatching in FIG.10(a), the die-bonding agent 20 such as solder paste is applied to afront part of the first lead 15, the second lead 22, the first frontelectrode piece 23 a and the second front electrode piece 23 b. Then,the diode chip 1 is placed onto the die-bonding agent 20, with the firstelectrode 2 and the second electrode 3 facing downward. In this state,the solder paste for example is heated up to a temperature no lower thanits melting point, and then the die-bonding agent 20 is allowed to coolfor solidification.

In the above-described procedure, the diode chip 1 may be slanted sothat the first side 1 a 1 and the fourth side 1 a 4 of the chip 1 arenonparallel to the edges 10 a, 10 b of the circuit substrate 10, asshownby the double-dot chain lines in FIG. 10(a), or the diode chip 1may be located at a position deviating from the center of the circuitsubstrate 10. In such a case, the surface tension of the thermallymelted solder (die-bonding agent) 20 acts simultaneously on therespective crossing portions between the leads 15, 22 and the sides 1 a1, 1 a 3 of the light-emitting diode chip 1, while also acting atbetween the surface of the front electrode pieces 23 a, 23 b and thesurface of the second electrode. Thus, by the self-alignment effect dueto the surface tension, the quadrangular diode chip 1 undergoesautomatic posture correction (see FIG. 8(b)) so that the crossing anglebetween the longitudinal direction of the first lead 15 and the firstside 1 a 1 of the diode chip 1 becomes generally 90° as viewed in plan.Likewise, the crossing angle between the longitudinal direction of thesecond lead 22 and the third side 1 a 3 becomes generally 90° as viewedin plan. Further, in the presence of the first front electrode piece 23a and the second front electrode piece 23 b, a proper electricalconnection is made with respect to the second electrode 3.

FIG. 11(a) and FIG. 11(b) show a sixth embodiment, wherein use is madeof the same leads as the leads 15, 22 of the fifth embodiment and aresist layer 21 formed around the diode chip 1 on the circuit substrate10. Thus, the advantages of the fifth embodiment and the advantages ofthe second embodiment (see FIG. 7(a) and FIG. 7(b)) can be enjoyed.

FIG. 12 shows a seventh embodiment, wherein the quadrangular crystalsubstrate 1 a of the diode chip 1 has a surface provided with a firstelectrode 2, formed in a generally central, small region close to oneside of the crystal substrate, and with a second electrode 3, facing thefirst electrode 2 and formed in a relatively large region extendingalong the other three sides of the substrate 1 a, the second electrodebeing laterally symmetrical in FIG. 12. The upper surface of the circuitsubstrate 10 is provided with, as described below, a first externalconnection electrode 12 and a second external connection electrode 13formed integral with the terminal electrodes 11, 12 at the respectiveends of the circuit substrate 10, wherein the electrodes 12, 13 areconnected to the first electrode 2 and the second electrode 3 via thedie-bonding agent 20 such as solder paste.

The electrode 11 is formed integral with a narrow first lead 24extending transversely to one side of the crystal substrate 1 a,whilethe electrode 12 is formed with a second lead 25 extending in theopposite direction to the extending direction of the first lead 24 tocross another side of the crystal substrate 1 a which is generallyparallel to the above-mentioned side crossed by the first lead 24. Thefront end of the second lead 25 is formed integral with a frontelectrode piece 25 a to be connected to the second electrode 3.

In the present embodiment, the first electrode 2 and the secondelectrode 3 of the diode chip 1 are laterally symmetrical, and the firstlead 24 and the second lead 25 are in line. Thus, the surface tension bythe melted solder acts simultaneously and with generally the samestrength (generally equally) both in the extending direction of thefirst lead 24 and the second lead 25 and in the perpendicular directionalong which the two opposing sides of the diode chip 1 (the crystalsubstrate 1 a) extend. Therefore, even if the diode chip 1 is placed onthe circuit substrate 10, with its sides are nonparallel to the left andright edges 10 a, 10 b of the circuit substrate 10, or even if the diodechip 1 is placed at a position deviating from the center of the circuitsubstrate 10, the self-alignment effect by the above-mentioned surfacetension makes it possible to automatically correct the posture of thediode chip 1, so that each of the side surfaces of the chip is parallelor generally parallel to the corresponding side of the quadrangularcircuit substrate 10. It is also possible to perform automaticcorrection for accurately positioning the diode chip 1 to the arealcenter of the circuit substrate 10.

Then, with the corrected posture, the diode chip 1 is fixed in positionas the melted solder solidifies.

Regarding the above-described embodiments, the inventors conducted someexperiments to discover that the automatic correction by theself-alignment resulting from the surface tension of the melted solderis reliably performed when the width of each lead is about 0.1-0.3 timesthe length of the sides of the diode chip 1, and this held for caseswhere use was made of the rmally meltable die-bonding agents other thanthe electroconductive solder paste.

In summary, the arrangements of the above-described embodiments make itpossible that the posture correction for the light-emitting diode chip 1to be die-bonded to the circuit substrate 10 is performed due to theself-alignment effect by the die-bonding process, so that the pairedside surfaces of the diode chip 1 become generally parallel to thelongitudinal direction of each lead on the circuit substrate 10. As aresult, the size of the mold 19 for packaging the diode chip 1 and thesize of the circuit substrate 10 can be made smaller than isconventionally possible, and accordingly the resultant chip LEDs arecompact and light. Further, it is possible to reduce the variations indirectivity of light emitted from light-emitting diode chips 1.

The above-described embodiments relate to a chip LED utilizing alight-emitting diode chip. However, the present invention is not limitedto chip LEDs, but applicable to other semiconductor devices includingdiodes, transistors, etc.

1. A semiconductor device utilizing a semiconductor chip, comprising, asemiconductor chip provided with: a first electrode formed in a smallregion at a first corner on one surface of a crystal substrate generallyquadrangular as viewed in plan; and a second electrode formed in a largeregion and facing the first electrode, the second electrode beingarranged to cover a second corner located diagonally away from the firstcorner and extend along two sides of the crystal substrate that includethe second corner, and a circuit substrate including an upper surfaceprovided with a pair of external connection electrodes connected to thefirst electrode and the second electrode via a thermally meltabledie-bonding agent such as solder paste, the external connectionelectrodes comprising: a first external connection electrode including afirst lead connected to the first electrode; and a second externalconnection electrode including a second lead connected to the secondelectrode, the first lead of the first external connection electrodebeing narrow and extending transversely to one side of the crystalsubstrate, the second lead of the second external connection electrodeincluding at least one narrow strip and extending in a directionopposite to the extending direction of the first lead, the second leadbeing transverse to another side of the crystal substrate that isgenerally parallel to said one side to which the first lead istransverse, and the first lead and the second lead being offset fromeach other by a prescribed distance.
 2. A semiconductor device utilizinga semiconductor chip, comprising, a semiconductor chip provided with: afirst electrode formed in a small region at a first corner on onesurface of a crystal substrate generally quadrangular as viewed in plan;and a second electrode formed in a large region and facing the firstelectrode, the second electrode being arranged to cover a second cornerlocated diagonally away from the first corner and extend along two sidesof the crystal substrate that include the second corner, and a circuitsubstrate including an upper surface provided with a pair of externalconnection electrodes connected to the first electrode and the secondelectrode via a thermally meltable die-bonding agent such as solderpaste, the external connection electrodes comprising: a first externalconnection electrode including a first lead connected to the firstelectrode; and a second external connection electrode including a secondlead connected to the second electrode, the first lead of the firstexternal connection electrode being narrow and extending transversely toone side of the crystal substrate, the second lead of the secondexternal connection electrode including at least one narrow strip andextending in a direction opposite to the extending direction of thefirst lead, the second lead being transverse to another side of thecrystal substrate that is generally parallel to said one side to whichthe first lead is transverse, and the second lead being provided, at anend thereof, with a front electrode piece which is connected to thesecond electrode and parallel to but offset by a prescribed distancefrom the first lead.
 3. A semiconductor device utilizing a semiconductorchip, comprising, a semiconductor chip provided with: a first electrodeformed in a small region at a central portion along one side on onesurface of a crystal substrate generally quadrangular as viewed in plan;and a second electrode formed in a large region and facing the firstelectrode, the second electrode extending along other three sides of thecrystal substrate, a circuit substrate including an upper surfaceprovided with a pair of external connection electrodes connected to thefirst electrode and the second electrode via a thermally meltabledie-bonding agent such as solder paste, the external connectionelectrodes comprising: a first external connection electrode including afirst lead connected to the first electrode; and a second externalconnection electrode including a second lead connected to the secondelectrode, the first lead of the first external connection electrodebeing narrow and extending transversely to one side of the crystalsubstrate, the second lead of the second external connection electrodeincluding at least one narrow strip and extending in a directionopposite to the extending direction of the first lead, the second leadbeing transverse to another side of the crystal substrate that isgenerally parallel to said one side to which the first lead istransverse.
 4. The semiconductor device utilizing a semiconductor chipaccording to claim 1, wherein the second lead of the second externalconnection electrode is provided, at an end thereof, with a frontelectrode piece extending at least in a direction transverse to thelongitudinal direction of the second lead and being connected to thesecond electrode.
 5. The semiconductor device utilizing a semiconductorchip according to claim 1, wherein the second external connectionelectrode is formed integral with a third lead, and wherein the thirdlead extends generally in parallel to another side of the crystalsubstrate that is transverse to the side to which the second lead istransverse, the third lead including an end which is transverse to saidanother side and connected to the second electrode.
 6. The semiconductordevice utilizing a semiconductor chip according to claim 5, wherein thefirst lead, the second lead and the third lead have a width which isabout 0.1-0.3 times a length of each of opposing sides of the crystalsubstrate.
 7. The semiconductor device utilizing a semiconductor chipaccording to claim 1, wherein the semiconductor chip comprises alight-emitting element and is at least packaged by a mold made oftransparent synthetic resin.
 8. The semiconductor device utilizing asemiconductor chip according to claim 1, wherein a resist layer isformed on parts of the first, second and third leads, the parts beingclose to a periphery of the semiconductor chip.
 9. The semiconductordevice utilizing a semiconductor chip according-to claim 2, wherein thesecond lead of the second external connection electrode is provided, atan end thereof, with a front electrode piece extending at least in adirection transverse to the longitudinal direction of the second leadand being connected to the second electrode.
 10. The semiconductordevice utilizing a semiconductor chip according-to claim 3, wherein thesecond lead of the second external connection electrode is provided, atan end thereof, with a front electrode piece extending at least in adirection transverse to the longitudinal direction of the second leadand being connected to the second electrode.
 11. The semiconductordevice utilizing a semiconductor chip according to claim 2, wherein thesecond external connection electrode is formed integral with a thirdlead, and wherein the third lead extends generally in parallel toanother side of the crystal substrate that is transverse to the side towhich the second lead is transverse, the third lead including an endwhich is transverse to said another side and connected to the secondelectrode.
 12. The semiconductor device utilizing a semiconductor chipaccording to claim 2, wherein the semiconductor chip comprises alight-emitting element and is at least packaged by a mold made oftransparent synthetic resin.
 13. The semiconductor device utilizing asemiconductor chip according to claim 3, wherein the semiconductor chipcomprises a light-emitting element and is at least packaged by a moldmade of transparent synthetic resin.
 14. The semiconductor deviceutilizing a semiconductor chip according to claim 2, wherein a resistlayer is formed on parts of the first, second and third leads, the partsbeing close to a periphery of the semiconductor chip.
 15. Thesemiconductor device utilizing a semiconductor chip according to claim3, wherein a resist layer is formed on parts of the first, second andthird leads, the parts being close to a periphery of the semiconductorchip.